4000S Datasheet, PDF (18/35 Pages) Cypress Semiconductor – 32-bit MCU Subsystem

PSoC^® 4: PSoC 4000S
Family Datasheet
Table 11. CSD and IDAC Specifications (continued)
SPEC ID#
SID315G
SID315H
SID320
Parameter
Description
Min Typ
IDAC3CRT23 Output current of IDAC in 8-bit mode 69
–
in medium range
IDAC3CRT33 Output current of IDAC in 8-bit mode 540
–
in high range
IDACOFFSET All zeroes input
–
–
SID321
IDACGAIN
Full-scale error less offset
–
–
SID322
IDACMISMATCH1 Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
SID322A
IDACMISMATCH2 Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
SID322B
IDACMISMATCH3 Mismatch between IDAC1 and
IDAC2 in High mode
–
–
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC –
–
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC –
–
SID325
CMOD
External modulator capacitor.
–
2.2
Max
Units Details / Conditions
82
µA LSB = 300-nA typ.
660
µA LSB = 2.4-µA typ.
1
LSB Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
±10
%
9.2
LSB LSB = 37.5-nA typ.
5.6
LSB LSB = 300-nA typ.
6.8
LSB LSB = 2.4-µA typ.
10
µs Full-scale transition. No
external load.
10
µs Full-scale transition. No
external load.
–
nF 5-V rating, X7R or NP0 cap.
Table 12. 10-bit CapSense ADC Specifications
Spec ID#
Parameter
SIDA94
A_RES
Description
Resolution
SIDA95
SIDA97
SIDA98
A_CHNLS_S
A-MONO
A_GAINERR
Number of channels - single
ended
Monotonicity
Gain error
Min Typ
–
–
–
–
–
–
–
–
SIDA99
A_OFFSET
Input offset voltage
–
–
SIDA100
SIDA101
SIDA103
SIDA104
SIDA106
A_ISAR
A_VINS
A_INRES
A_INCAP
A_PSRR
Current consumption
Input voltage range - single
ended
Input resistance
Input capacitance
Power supply rejection ratio
–
–
V_SSA
–
–
2.2
–
20
–
60
SIDA107
A_TACQ
Sample acquisition time
–
1
SIDA108
A_CONV8
Conversion time for 8-bit
–
–
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
SIDA108A A_CONV10
Conversion time for 10-bit
–
–
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
Max
10
16
–
±2
3
0.25
V_DDA
–
–
–
–
21.3
85.3
Units Details/Conditions
bits Auto-zeroing is required
every millisecond
Defined by AMUX Bus.
Yes
% In V_REF (2.4 V) mode
with V_DDA bypass capac-
itance of 10 µF
mV In V_REF (2.4 V) mode
with V_DDA bypass capac-
itance of 10 µF
mA
V
KΩ
pF
dB In V_REF (2.4 V) mode
with V_DDA bypass capac-
itance of 10 µF
µs
µs Does not include acqui-
sition time. Equivalent to
44.8 ksps including
acquisition time.
µs Does not include acqui-
sition time. Equivalent to
11.6 ksps including
acquisition time.
Document Number: 002-00123 Rev. *I
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