W48S87-04 Datasheet, PDF (20/21 Pages) Cypress Semiconductor – Spread Spectrum 3 DIMM Desktop Clock

PRELIMINARY
W48S87-04
2.5V AC Electrical Characteristics (CPU3.3#_2.5 Input = 1)
T_A = 0°C to +70°C, VDD1:3 = 3.3V±5% (3.135–3.465V), VDDL1:2 = 2.5V±5% (2.375–2.625V),
f_XTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
t_H
High Time
Duration of clock cycle above 2.0V
5.2
6
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5
5.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
0.8
3 0.8
3 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
0.8
3 0.8
3 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
250
250 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi- 12 20 30 12 20 30 Ω
tion. Used for determining series termi-
nation value.
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
10
15
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Freq. Mask
Code
W48S87
04
Document #: 38-00859
Package
Name
H
Package Type
48-pin SSOP (300 mils)
20