W48S87-04 Datasheet, PDF (18/21 Pages) Cypress Semiconductor – Spread Spectrum 3 DIMM Desktop Clock

PRELIMINARY
W48S87-04
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t_R
t_F
t_D
f_ST
Z_o
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
8
12
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
40
60
1.5
17
20
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
40
55
1.5
20
25
35
Unit
MHz
V/ns
V/ns
%
ms
Ω
18