W48S87-04 Datasheet, PDF (2/21 Pages) Cypress Semiconductor – Spread Spectrum 3 DIMM Desktop Clock

PRELIMINARY
W48S87-04
Pin Definitions
Pin Name
CPU0:3
PCI_F/FS1
PCI0/FS2
PCI1:4
PCI5(PWR_DWN#)
SDRAM0:11
IOAPIC
48MHZ/FS0
24MHZ/MODE
Pin
No.
44, 43, 41,
40
7
8
10, 11, 12,
13
15
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
47
26
25
Pin
Type
O
I/O
I/O
O
I/O
O
Pin Description
CPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled
by the CPU_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDL2 and output characteristics are adjusted by input
CPU3.3#_2.5.
Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this
pin works in conjunction with PCI0:5. Output voltage swing is controlled by
voltage applied to VDD2.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up default frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI Bus Clock Output 0 and Frequency Selection Bit 2: As an output, this
pin works in conjunction with PCI1:5 and PCI_F. Output voltage swing is con-
trolled by voltage applied to VDD2.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up default frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by
voltage applied to VDD2.
PCI Bus Clock Output 5 or Power-Down Control: As an output, this pin works
in conjunction with PCI0:4 and PCI_F. Output voltage swing is controlled by
voltage applied to VDD2.
If programmed as an input (refer to MODE pin description), this pin is used for
power-down control. When LOW, the device goes into a low-power standby
condition. All outputs are actively held LOW while in power-down. CPU,
SDRAM, and PCI clock outputs are stopped LOW after completing a full clock
cycle (2–4 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and
PCI outputs start with a full clock cycle at full operating frequency (3 ms max-
imum latency).
SDRAM Clock Outputs 0 through 11: These twelve SDRAM clock outputs
run synchronous to the CPU clock outputs. Output voltage swing is controlled
by voltage applied to VDD3.
O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output
voltage swing is controlled by VDDL1.
I/O 48-MHz Output and Frequency Selection Bit 0: Fixed clock output that de-
faults to 48 MHz following device power-up. Output voltage swing is controlled
by voltage applied to VDD1.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up default frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
I/O 24-MHz Output and Mode Control Input: Fixed clock output that defaults to
24 MHz following device power-up. Output voltage swing is controlled by volt-
age applied to VDD1.
When an input, this pin is used for pin programming selection. It determines
the functions for pins 15 and 46:
MODE
Pin 15
Pin 46
0
PWR_DWN# (input) CPU_STOP# (input)
1
PCI5 (output)
REF1 (output)
2