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W48S87-04 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – Spread Spectrum 3 DIMM Desktop Clock
PRELIMINARY
W48S87-04
Spread Spectrum 3 DIMM Desktop Clock
Features
• Outputs
— 4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz)
— 7 PCI (3.3V)
— 1 48-MHz for USB (3.3V)
— 1 24-MHz for Super I/O (3.3V)
— 2 REF (3.3V)
— 1 IOAPIC (2.5V or 3.3V)
— 12 SDRAM
• Serial data interface provides additional frequency
selection, individual clock output disable, and other
functions
• Smooth transition supports dynamic frequency
assignment
• Frequency selection not affected during power
down/up cycle
• Supports a variety of power-saving options
• 3.3V operation
• Available in 48-pin SSOP (300 mils)
Key Specifications
±0.5% Spread Spectrum Modulation: ......................... ±0.5%
Jitter (Cycle-to-Cycle): .................................................250 ps
Duty Cycle: ................................................................ 45-55%
CPU-PCI Skew: ........................................................ 1 to 4 ns
PCI-PCI or CPU-CPU Skew: .......................................250 ps
Table 1. Pin Selectable Frequency[1]
Input Address
FS2 FS1 FS0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
0
0
0
50.0
25.0
0
0
1
75.0
32.0
0
1
0
83.3
41.65
0
1
1
68.5
34.25
1
0
0
55.0
27.5
1
0
1
75.0
37.5
1
1
0
60.0
30.0
1
1
1
66.8
33.4
Block Diagram
Pin Configuration[2]
SDATA
SCLOCK
X1
X2
CPU3.3#_2.5
FS0
FS1
FS2
CPU_STOP#
Serial Port
XTAL OSC
Device
Control
PLL Ref
Freq
VDD1
CPU Clock
Mode Control
Freq
Select
I/O
MODE
REF0/CPU3.3#_2.5
REF1(CPU_STOP#)
VDDL1
PLL1
Stop
Clock
Cntrl
IOAPIC
VDDL2
4 CPU0:3
VDD3
12 SDRAM0:11
÷2
VDD2
VDD1 1
REF0/CPU3.3#_2.5 2
GND 3
X1 4
X2 5
VDD2 6
PCI_F/FS1 7
PCI0/FS2 8
GND 9
PCI1 10
PCI2 11
PCI3 12
PCI4 13
VDD2 14
PCI5(PWR_DWN#) 15
GND 16
SDRAM11 17
SDRAM10 18
VDD3 19
SDRAM9 20
SDRAM8 21
GND 22
SDATA 23
SCLOCK 24
I/O PCI_F/FS1
I/O PCI0/FS2
4 PCI1:4
PWR_DWN#
Power Down MODE
Control
PCI5(PWR_DWN#)
VDD1
÷2
PLL2
÷4
I/O 48MHZ/FS0
I/O 24MHZ/MODE
Notes:
1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10.
2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.
48 VDDL1
47 IOAPIC
46 REF1(CPU_STOP#)
45 GND
44 CPU0
43 CPU1
42 VDDL2
41 CPU2
40 CPU3
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 GND
26 48MHZ/FS0
25 24MHZ/MODE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 19, 1999, rev. **