W48S87-04 Datasheet, PDF (17/21 Pages) Cypress Semiconductor – Spread Spectrum 3 DIMM Desktop Clock

PRELIMINARY
W48S87-04
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
SDRAM Clock Outputs, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.5V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.5V
100
100
ps
t_SK
CPU to SDRAM Clock Covers all CPU/SDRAM outputs. Mea-
500
Skew
sured on rising edge at 1.5V.
500 ps
f_ST
Frequency Stabilization Assumes full supply voltage reached
3
from Power-up (cold within 1 ms from power-up. Short cy-
start)
cles exist prior to frequency stabiliza-
tion.
3 ms
Z_o
AC Output Impedance Average value during switching transi- 10 15 20 10 15 20 Ω
tion. Used for determining series ter-
mination value.
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz CPU = 60 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.5V
30
33.3
ns
f
Frequency, Actual
Determined by PLL divider ratio
33.4
29.938
MHz
t_H
High Time
Duration of clock cycle above 2.4V
12
13.3
ns
t_L
Low Time
Duration of clock cycle below 0.4V
12
13.3
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.5V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Mea-
1
sured on rising edge at 1.5V. CPU
leads PCI output.
250
41
250 ps
4 ns
f_ST
Frequency Stabilization Assumes full supply voltage reached
3
from Power-up (cold within 1 ms from power-up. Short cy-
start)
cles exist prior to frequency stabiliza-
tion.
3 ms
Z_o
AC Output Impedance Average value during switching transi- 15 20 30 15 20 30 Ω
tion. Used for determining series termi-
nation value.
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