CY8C20X34 Datasheet, PDF (185/218 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

20.4.3
SPI_CFG
SPI Configuration Register
SPI_CFG
1,29h
Individual Register Names and Addresses:
SPI_CFG : 1,29h
7
6
5
Access : POR
RW : 0
Bit Name
Clock Sel
1,29h
4
RW : 0
Bypass
3
RW : 0
SS_
2
RW : 0
SS_EN_
1
RW : 0
Int Sel
0
RW : 0
Slave
This register is used to configure the SPI.
The values in this register should not be changed while the block is enabled.
For additional information, refer to the Register Definitions on page 119 in the SPI chapter.
Bit
Name
7:5
Clock Sel
4
Bypass
3
SS_
2
SS_EN_
1
Int Sel
0
Slave
Description
SYSCLK in Master mode
000b / 2
001b / 4
010b / 8
011b / 16
100b / 32
101b / 64
110b / 128
111b / 256
Bypass Synchronization
0
All pin unputs are doubled, synchronized
1
Input synchronization is bypassed.
Slave Select in Slave mode
0
Slave selected
1
Slave not selected
Internal Slave Select Enable
0
Slave selection determined from SS_ bit
1
Slave selection determined from external SS_ pin
Interrupt Select
0
Interrupt on TX Reg Empty
1
Interrupt on SPI Complete
0
Operates as a master.
1
Operates as a slave.
PSoC CY8C20x34 TRM, Version 1.0
185