CY8C20X34 Datasheet, PDF (168/218 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

MVR_PP
0,D4h
20.3.28 MVR_PP
MVI Read Page Pointer Register
Individual Register Names and Addresses:
MVR_PP: 0,D4h
0,D4h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
Page Bit
This register is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the Register Definitions on page
36 in the RAM Paging chapter.
Bit
Name
0
Page Bit
Description
Bit determines which SRAM page a MVI Read instruction operates on.
0b
SRAM Page 0
1b
SRAM Page 1
Note A value beyond the available SRAM, for a specific PSoC device, should not be set.
168
PSoC CY8C20x34 TRM, Version 1.0