CY8C20X34 Datasheet, PDF (115/218 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

17. POR and LVD
This chapter briefly discusses the Power on Reset (POR) and Low Voltage Detect (LVD) circuits and their associated regis-
ters. For a complete table of the POR registers, refer to the “Summary Table of the System Resource Registers” on page 90.
For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 139.
17.1 Architectural Description
The Power on Reset (POR) and Low Voltage Detect (LVD) circuits provide protection against low voltage conditions. The
POR function senses Vdd and holds the system in reset until the magnitude of Vdd will support operation to specification. The
LVD function senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold. Other outputs
and status bits are provided to indicate important voltage trip levels. Refer to Section 16.2 Pin Behavior During Reset for a
description of GPIO pin behavior during power up.
17.2 Register Definitions
The following registers are associated with the POR and LVD, and are listed in address order. The register descriptions below
have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits
and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. For a
complete table of the POR registers, refer to the “Summary Table of the System Resource Registers” on page 90.
17.2.1 VLT_CR Register
Address Name
1,E3h VLT_CR
Bit 7
Bit 6
Bit 5
Bit 4
PORLEV[1:0]
Bit 3
LVDTBEN
Bit 2
Bit 1
VM[2:0]
Bit 0
Access
RW : 00
The Voltage Monitor Control Register (VLT_CR) is used to
set the trip points for POR and LVD.
The VLT_CR register is cleared by all resets. This can cause
reset cycling during very slow supply ramps to 5V when the
POR range is set for the 5V range. This is because the reset
clears the POR range setting back to 3V and a new boot/
start-up occurs (possibly many times). The user can man-
age this with Sleep mode and/or reading voltage status bits
if such cycling is an issue.
Bits 5 and 4: PORLEV[1:0]. These bits set the Vdd level at
which PPOR switches to one of three valid values. Note that
11b is a reserved value and should not be used.
The three valid settings for these bits are:
❐ 00b (2.4V operation)
❐ 01b (2.7V operation)
❐ 10b (3.0V operation)
See the “DC POR and LVD Specifications” table in the Elec-
trical Specifications section of the PSoC device data sheet
for voltage tolerances for each setting.
Bit 3: LVDTBEN. This bit is AND’ed with LVD to produce a
throttle-back signal that reduces CPU clock speed when low
voltage conditions are detected. When the throttle-back sig-
nal is asserted, the CPU speed bits in the OSC_CR0 regis-
ter are reset forcing the CPU speed to its reset state.
Bits 2 to 0: VM[2:0]. These bits set the Vdd level at which
the LVD Comparator switches.
See the “DC POR and LVD Specifications” table in the Elec-
trical Specifications section of the PSoC device data sheet
for voltage tolerances for each setting.
For additional information, refer to the VLT_CR register on
page 191.
PSoC CY8C20x34 TRM, Version 1.0
115