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MB39C015 Datasheet, PDF (13/43 Pages) Cypress Semiconductor – High efficiency : 96% (Max) | |||
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MB39C015
(Continued)
(Ta ï½ ï«25 °C , AVDD ï½ DVDD1 ï½ DVDD2 ï½ 3.7 V, VOUT1/VOUT2 setting value ï½ 2.5 V, MODE1/MODE2 ï½ 0 V)
Parameter
Symbol Pin No.
Condition
Value
Unit
Min
Typ
Max
Control block
CTL threshold
voltage
CTL pin
input current
VTHHCT
VTHLCT
IICTL
1, 2, 3
â
â
0 V ï£ CTLP/CTL1/CTL2 ï£
3.7 V
0.55 0.95 1.45 V
0.40 0.80 1.30 V
â
â
1.0
ïA
Reference
voltage block
VREF voltage
VREF Load
stability
VREF
6
LOADREF
VREF ï½ 0 mA
VREF ï½ ï1.0 mA
1.274 1.300 1.326 V
â
â
20
mV
Shut down
power supply
current
IVDD1
IVDD1H
CTLP/CTL1/CTL2 ï½ 0 V
â
â
1.0
ïA
State of all circuits OFF*3
CTLP/CTL1/CTL2 ï½ 0 V,
â
â
1.0
ïA
VDD ï½ 5.5 V
State of all circuits OFF*3
General
Power supply current IVDD31
(DC/DC mode)
IVDD32
5, 11,
12, 19,
20
1. CTLP ï½ 0 V, CTL1 ï½ 3.7 V, â
CTL2 ï½ 0 V
2. CTLP ï½ 0 V, CTL1 ï½ 0 V,
CTL2 ï½ 3.7 V
OUT ï½ 0 A
CTLP ï½ 0 V, CTL1/CTL2 ï½
â
3.7 V, OUT ï½ 0 A
3.5
10
mA
7.0
20.0 mA
Power supply current IVDD5
(voltage detection
mode)
CTLP ï½ 3.7 V,
CTL1/CTL2 ï½ 0 V,
â
15
24
ïA
Power-on
IVDD
invalid current
1. CTL1 ï½ 3.7 V, CTL2 ï½ 0 V â
2. CTL1 ï½ 0 V, CTL2 ï½ 3.7 V
VOUT1/VOUT2 ï½ 90%
OUT ï½ 0 A*4
1000 2000 ïA
*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher.
*2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.
*3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.
*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included
because the device is in full ON state (no switching operation). Also the load current is not included.
Document Number: 002-08364 Rev. *A
Page 13 of 43
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