FX919A Datasheet, PDF (27/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX919A
Status Register B3: CRCERR - CRC Checksum Error
In receive mode this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the
receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error.
Note that this bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task, or by changing the TXRXN or PSAVE bits of the Mode Register. In
transmit mode this bit is '0'.
Status Register B2, B1, B0
These bits are reserved for future use.
1.5.5.6 Data Quality Register
In receive mode, the FX919A continually measures the 'quality' of the received signal, by comparing the actual
received waveform over the previous 64 symbol times against an internally generated 'ideal'.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 14 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
250
200
150
DQ
100
50
0
5
7
9
11
13
15
S/N dB (noise in 2* symbol-rate bandwidth)
Figure 14 Typical Data Quality Reading vs S/N
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing
lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when
the LEVRES setting is 'Clamp' or 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set
to 'Wide' or if the received signal waveform is distorted in any significant way.
© 1996 Consumer Microcircuits Limited
27
D/919A/4