FX919A Datasheet, PDF (17/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX919A
NULL: No effect
This 'task' is provided so that a AQSC or AQLEV command can be initiated without loading a new task.
SFSH: Search for Frame Sync plus Header Block
This task causes the modem to search the received signal for a valid 24-symbol Frame Sync sequence
followed by Header Block which has a correct CRC1 checksum.
The task continues until a valid Frame Sync plus Header Block has been found.
The search consists of two stages:
First of all the modem will attempt to match the incoming symbols against the 24-symbol Frame
Synchronisation pattern to within the tolerance defined by the FSTOL bits of the Control Register.
Once a match has been found, the modem will read in the next 66 symbols as if they were a 'Header'
block, decoding the symbols and checking the CRC1 checksum. If this is incorrect, the modem will
resume the search, looking for a fresh Frame Sync pattern.
If the received CRC1 is correct, the 10 decoded data bytes will be placed into the Data Block Buffer,
the BFREE and IRQ bits of the Status Register will be set to '1' and the CRCERR bit cleared to '0'.
On detecting that the BFREE bit of the Status Register has gone to '1', the µC should read the 10 bytes from
the Data Block Buffer then write the next task to the modem's Command Register.
RHB: Read Header Block
This task causes the modem to read the next 66 symbols as a 'Header' Block, decoding them, placing the
resulting 10 data bytes and the 2 received CRC1 bytes into the Data Block Buffer, and setting the BFREE and
IRQ bits of the Status Register to '1' when the task is complete to indicate that the µC may read the data from
the Data Block Buffer and write the next task to the modem's Command Register.
The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1
checksum bytes.
RILB: Read 'Intermediate' or 'Last' Block
This task causes the modem to read the next 66 symbols as an 'Intermediate' or 'Last' block (the µC should be
able to tell from the 'Header' block how many blocks are in the frame, and hence when to expect the 'Last'
block).
In each case, it will decode the 66 symbols and place the resulting 12 bytes into the Data Block Buffer, setting
the BFREE and IRQ bits of the Status Register to '1' when the task is complete.
If an 'Intermediate' block is received then the µC should read out all 12 bytes from the Data Block Buffer and
ignore the CRCERR bit of the Status Register, for a 'Last' block the µC need only read the first 8 bytes from the
Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2
checksum.
SFS: Search for Frame Sync
This task causes the modem to search the received signal for a 24-symbol sequence which matches the Frame
Synchronisation pattern to within the tolerance defined by the FSTOL bits of the Mode Register.
When a match is found the modem will set the BFREE and IRQ bits of the Status Register to '1' to indicate to
the µC that it should write the next task to the Command Register.
© 1996 Consumer Microcircuits Limited
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D/919A/4