FX919A Datasheet, PDF (13/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX919A
The 'Header' block is self-contained in that it includes its own checksum (CRC1), and would normally carry
information such as the addresses of the called and calling parties, the number of following blocks in the frame
(if any) and miscellaneous control information. The 'Intermediate' block(s) contain only data, the checksum for
all of the data in the 'Intermediate' and 'Last' blocks (CRC2) being contained at the end of the 'Last' block.
This arrangement, whilst efficient in terms of data capacity, may not be optimum for poor signal-to-noise
conditions, since a reception error in any one of the 'Intermediate' or 'Last' blocks would invalidate the whole
frame. In these conditions, increased throughput may be obtained by using the 'Header' block format for all
blocks of the frame, so that blocks which are received correctly can be identified as such, and need not be re-
transmitted. This, and some other possible frame structures, are shown in Figure 7a below.
Figure 7a Some Alternative Frame Structures
The FX919A performs all of the block formatting and de-formatting, the binary data transferred between the
modem and its µC being that enclosed by the thick dashed rectangles near the top of Figure 7.
1.5.5 The Programmer's View
The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers,
individual registers being selected by the A0 and A1 chip inputs:
A1 A0
00
01
10
11
Write to Modem
Data Buffer
Command Register
Control Register
Mode Register
Read from Modem
Data Buffer
Status Register
Data Quality Register
not used
Note that there is a minimum allowable time between accesses of the modem's registers, see Section 1.7.1 for
details.
1.5.5.1 Data Block Buffer
This is a 12-byte read/write buffer which is used to transfer data (as opposed to command, status, mode, data
quality or control information) between the modem and the host µC.
It appears to the µC as a single 8-bit register; the modem ensuring that sequential µC reads or writes to the
buffer are routed to the correct locations within the buffer.
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.
The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive
mode the modem will function correctly even if the received data is not read from the Data Buffer by the µC.
© 1996 Consumer Microcircuits Limited
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D/919A/4