FX919A Datasheet, PDF (24/44 Pages) CML Microcircuits – 4-Level FSK Modem Data Pump

4-Level FSK Modem Data Pump
FX919A
The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the
frequency of the receiving modem's Xtal are both within ±100ppm of nominal, except at the start of a symbol
clock acquisition sequence (AQSC) when 'WIde Bandwidth' should be selected as described in section 1.6.3.
If the received symbol rate and Xtal frequency are both within ±20ppm of nominal then selection of the 'Narrow
Bandwidth' setting will give better performance, especially through fades or noise bursts which might otherwise
pull the PLL away from its optimum timing, but in this case it is recommended that the PLLBW bits are only set
to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth' mode for about 200 symbol
times.
The 'Hold' setting disables the feedback loop of the PLL, which continues to run at a rate determined only by
the actual Xtal frequency and the setting of the Control Register CKDIV bits.
1.5.5.4 Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register B7: IRQNEN - IRQN Output Enable
When this bit is set to '1', the IRQN chip output pin is pulled low (to Vss) whenever the IRQ bit of the Status
Register is a '1'.
Mode Register B6: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
B6 Symbol
0
'+3'
'-3'
1
'+3'
'-3'
Signal at TXOP
Above V_BIAS
Below V_BIAS
Below V_BIAS
Above V_BIAS
Signal at RXFB
Below V_BIAS
Above V_BIAS
Above V_BIAS
Below V_BIAS
Mode Register B5: TXRXN - Tx/Rx Mode
Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode.
Note that changing between receive and transmit modes will cancel any current task.
© 1996 Consumer Microcircuits Limited
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D/919A/4