CDB4265 Datasheet, PDF (9/30 Pages) Cirrus Logic – Evaluation Board for CS4265

CDB4265
3.3 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS4265, CS8416,
and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or byte-
wise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired hex value
can be typed directly in the register address box in the register map.
Figure 3. Register Maps Tab
3.4 Pre-Configured Script Files
Pre-configured script files are provided with the CDB4265 to allow easy initial board bring-up. The board
configurations stored within these files are described in sections 3.4.1 - 3.4.2.
3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out
Using the pre-configured script file named “Oscillator Clock - Line In to DAC & SPDIF Out.txt”, an analog
input signal applied to the line level inputs of the CS4265 input multiplexer will be digitized by the ADC, trans-
mitted in S/PDIF format by the CS4265 internal S/PDIF transmitter, and converted to analog by the DAC
and output through the passive output filter.
The canned oscillator is the source of MCLK. The CS4265 is the sub-clock master to the PCM I/O header.
DS657DB1
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