CDB4265 Datasheet, PDF (12/30 Pages) Cirrus Logic – Evaluation Board for CS4265

5. FPGA REGISTER DESCRIPTION
CDB4265
5.1 CODE REVISION ID - REGISTER 01H
7
Rev7
6
Rev6
5
Rev5
4
Rev4
3
Rev3
2
Rev2
Function:
Identifies the revision of the FPGA code. This register is Read-Only.
1
Rev1
0
Rev0
5.2 MCLK SOURCE CONTROL - ADDRESS 02H
7
Reserved
6
Reserved
5
MCLK1
4
MCLK0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
5.2.1 MCLK SOURCE (BITS 5:4)
Default = 10
Function:
These bits select the source of the CS4265 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK1
0
0
1
1
MCLK0
0
1
0
1
MCLK Source
Oscillator
MCLK position on PCM Header (J15)
CS8416 RMCK
Reserved
12
DS657DB1