CDB4265 Datasheet, PDF (10/30 Pages) Cirrus Logic – Evaluation Board for CS4265

CDB4265
3.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out
Using the pre-configured script file named “SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF
Out.txt”, an analog input signal applied to the line level inputs of the CS4265 input multiplexer will be digi-
tized by the ADC and transmitted in S/PDIF format by the CS4265 internal S/PDIF transmitter. The S/PDIF
signal received by the CS8416 will be recovered, decoded into PCM, and routed to the CS4265 DAC where
it will be converted to analog by the DAC and output through the passive output filter. For proper operation
of this script, a valid S/PDIF signal must be applied.
The CS8416 recovered clock is the source of MCLK. The CS8416 is also the sub-clock master to the
CS4265 and the PCM I/O header.
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DS657DB1