CDB4265 Datasheet, PDF (4/30 Pages) Cirrus Logic – Evaluation Board for CS4265

CDB4265
1. SYSTEM OVERVIEW
The CDB4265 evaluation board is an excellent means for evaluating the CS4265 CODEC. Analog and digital audio
signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluation platform, and a 9-pin
serial cable is included for use with the supplied Windows^® configuration software.
The CDB4265 schematic set is shown in Figures 5 through 12.
1.1 Power
Power must be supplied to the evaluation board through the red +5.0 V binding post. On-board regulators
provide 3.3 V, 2.5 V, and 1.8 V supplies. Appropriate supply levels for powering VA, VD, VLS, and VLC are
set by a series of jumpers (see Table 7 on page 17). All voltage inputs must be referenced to the single black
binding post ground connector (see Table 6 on page 16).
WARNING: Please refer to the CS4265 data sheet for allowable voltage levels.
1.2 Grounding and Power Supply Decoupling
The CS4265 requires careful attention to power supply and grounding arrangements to optimize perfor-
mance. Figure 4 on page 18 provides an overview of the connections to the CS4265. Figure 13 on page 27
shows the component placement. Figure 14 on page 28 shows the top layout. Figure 15 on page 29 shows
the bottom layout. The decoupling capacitors are located as close to the CS4265 as possible. Extensive use
of ground plane fill in the evaluation board yields large reductions in radiated noise.
1.3 CS4265 Audio CODEC
A complete description of the CS4265 is included in the CS4265 product data sheet.
The required configuration settings of the CS4265 are made in its control port registers, accessible through
the CS4265 tab of the Cirrus Logic FlexGUI software.
Clock and data source selections are made through the control port of the FPGA. Basic routing selections
can be made using the CS4265 Controls tab in the GUI software application. Advanced options are acces-
sible through the Board Configuration sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI soft-
ware. Refer to the FPGA register descriptions sections beginning on page 12.
1.4 CS8416 Digital Audio Receiver
A complete description of the CS8416 receiver (Figure 8 on page 22) and a discussion of the digital audio
interface are included in the CS8416 data sheet.
The CS8416 converts the input S/PDIF data stream into PCM data for the CS4265 and operates in master
or slave mode, generating either a 128 Fs or 256 Fs master clock on the RMCK output pin, and can operate
in the Left-Justified, I²S, Right-Justified 16-bit, and Right-Justified 24-bit interface formats.
The most common operations of the CS8416 may be controlled via the S/PDIF Rx Controls tab in the GUI
software application. Advanced options are accessible through the CS8416 sub-tab on the Register Maps
tab of the Cirrus Logic FlexGUI software.
1.5 FPGA
The FPGA handles both clock and data routing on the CDB4265. Clock and data routing selections made
via the CDB4265 Controls tab in the GUI will be handled by the FPGA with no user intervention required.
For advanced information regarding the internal registers and operation of the FPGA, see sections 4 and 5
beginning on page 11.
1.6 Canned Oscillator
A canned oscillator, Y1, is available to provide a master clock source to the CDB4265.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with
a 12.2880 MHz crystal oscillator populated.
4
DS657DB1