CDB4265 Datasheet, PDF (13/30 Pages) Cirrus Logic – Evaluation Board for CS4265

CDB4265
5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
SUBCLK1
0
SUBCLK0
5.3.1 SUBCLOCK SOURCE (BITS 1:0)
Default = 01
Function:
This bit selects the source of the CS4265 SCLK and LRCK signals. Table 2 shows the available set-
tings.
Table 2. CS4265 Subclock Source
SUBCLK1 SUBCLK0
0
0
0
1
1
0
1
1
CS4265 Subclock Source
- CS4265 is Master
- PCM Header Subclocks are Output from CS4265
Reserved
- CS4265 is Slave to PCM Header
- PCM Header Subclocks are an Input
- CS4265 is Slave to CS8416 subclocks
- PCM Header Subclocks are Output from CS8416 Subclocks
DS657DB1
13