CS42516 Datasheet, PDF (80/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
10.1.3 Capacitor Selection
The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large
or exotic film capacitors are not necessary because their leads, and the required longer circuit board trac-
es, add undesirable inductance to the circuit. Surface-mount ceramic capacitors are a good choice be-
cause their own inductance is low, and they can be mounted close to the LPFLT pin to minimize trace
inductance. For CRIP, a C0G or NPO dielectric is recommended; and for CFILT, an X7R dielectric is pre-
ferred. Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants,
that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics.
10.1.4 Circuit Board Layout
Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure
30 illustrates a suggested layout for the PLL filter components and for bypassing the analog supply volt-
age. The 10 µF bypass capacitor is an electrolytic in a surface-mount case A or thru-hole package. RFILT,
CFILT, CRIP, and the 0.1 µF decoupling capacitor are in an 0805 form factor. The 0.01 µF decoupling
capacitor is in the 0603 form factor. The traces are on the top surface of the board with the IC so that there
is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The
VARX and AGND traces extend back to their origin and are shown only in truncated form in the drawing.
CRIP
0.01 µF
CFILT
0.1 µF
= via to ground plane
10 µF
Figure 30. Recommended Layout Example
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DS583F1