CS42516 Datasheet, PDF (41/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
4.10 Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42516 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 5 shows the recommended power ar-
rangements, with VA and VARX connected to clean supplies. VD, which powers the digital circuitry, may be
run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite
bead. In this case, no additional devices should be powered from VD.
For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog
+5 V supply for VARX, decoupled to AGND. In addition, a separate region of analog ground plane around
the FILT+, VQ, LPFLT, REFGND, AGND, VA, VARX, RXP/and RXP0 pins is recommended.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42516 as pos-
sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42516 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and
PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from FILT+ and REFGND. The CDB42518 evaluation board demonstrates the optimum lay-
out and power supply arrangements.
DS583F1
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