CS42516 Datasheet, PDF (25/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

4.5
CS42516
Clock Generation
The clock generation for the CS42516 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL
lock to the other source input.
RMCK_DIVx bits
Recovered
S/PDIF Clock
0
SAI_LRCK
(slave mode) ₁
PLL (256Fs)
8.192 -
49.152 MHz
OMCK
PLL_LRCK bit
Internal
MCLK
00
2 01
4 10
X2 11
00
Auto Detect
Input Clock
01
1,1.5, 2, 4
SW_CTRLx bits
(manual or auto
switch)
single
speed
256
double
speed
128
quad
speed
64
single
speed
4
RMCK
00
01
CX_LRCK
10
CODEC_FMx bits
00
DAC_OLx
or ADC_OLx bits
01
10
not OLM
128FS _{OLM #1}
CX_SCLK
256FS _{OLM #2}
double
speed
2
quad
speed
1
00
01
10
SAI_FMx bits
SAI_LRCK
00
ADC_OLx and
ADC_SP SELx bits
01
10
not OLM
128FS _{OLM #1}
SAI_SCLK
256FS _{OLM #2}
Figure 9. CS42516 Clock Generation
4.5.1
PLL and Jitter Attenuation
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming S/PDIF data stream.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is im-
portant. For this reason, the PLL has been designed to have good jitter attenuation characteristics as
shown in Figure 28 on page 79.
The PLL can be configured to lock onto the incoming SAI_LRCK signal from the Serial Audio Interface
Port and generate the required internal master clock frequency. By setting the PLL_LRCK bit to a ‘1’ in
the register “Clock Control (address 06h)” on page 53, the PLL will lock to the incoming SAI_LRCK and
generate an output master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input
Fs values for SAI_LRCK.
See “Appendix C: PLL Filter” on page 77 for more information concerning PLL operation, required filter
components, optimal layout guidelines, and jitter-attenuation characteristics.
DS583F1
25