CS42516 Datasheet, PDF (52/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
6.6.3
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
6.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)
Default = 0
Function:
This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off.
For filter characteristics, please See “D/A Digital Filter Characteristics” on page 11.
0 - Fast roll-off.
1 - Slow roll-off.
6.6.5
HIGH-PASS FILTER FREEZE (HPF_FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig-
ital Filter Characteristics” on page 9.
6.6.6 CODEC SERIAL PORT MASTER/SLAVE SELECT (CODEC_SP M/S)
Default = 0
Function:
In Master Mode, CX_SCLK and CX_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave Mode, CX_SCLK and CX_LRCK become in-
puts.
If the CX_SP is in Slave Mode, CX_LRCK must be present for proper device operation.
6.6.7
SERIAL AUDIO INTERFACE SERIAL PORT MASTER/SLAVE SELECT (SAI_SP M/S)
Default = 0
Function:
In Master Mode, SAI_SCLK and SAI_LRCK are outputs. Internal dividers will divide the master clock
to generate the serial clock and left/right clock. In Slave Mode, SAI_SCLK and SAI_LRCK become
inputs.
If the SAI_SP is in Slave Mode, SAI_LRCK must be present for proper device operation.
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