CS42516 Datasheet, PDF (77/91 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42516
10.APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information to
the PLL. This results in the PLL being immune to data-dependent jitter effects because the S/PDIF preambles do
not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. The
nominal center sample rate is the sample rate that the PLL first locks onto upon application of an S/PDIF data
stream.
INPUT
Phase
Comparator
and Charge Pump
RFILT
CFILT
VCO
CRIP
RMCK
÷N
Figure 27. PLL Block Diagram
10.1 External Filter Components
10.1.1 General
The PLL behavior is affected by the external filter component values and the locking mode as configured
by the LOCKM[1:0] bits in register 24h. Table 21 shows the supported configurations of PLL component
values and their associated locking modes.
Configuration 1
Configuration 2
Configuration 3
RFILT (kΩ) CFILT (µF) CRIP (pF) LOCKM[1:0]
Notes
2.55
0.047
2200
00
Used for backward compatibility with Revision C
devices.
2.55
0.047
2200
Default configuration for Revision D devices.
01
Provides improved wideband jitter rejection in
Double- and Quad-Speed modes.
1.37
0.022
1000
Provides improved in-band jitter rejection, with
10
increased wideband jitter. Use this configuration
for best DAC and ADC performance when
clocked from the PLL recovered clock.
Table 21. External PLL Component Values & Locking Modes
DS583F1
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