CS4228A_03 Datasheet, PDF (8/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VL)
Parameter
Symbol
Min
Audio ADC's and DAC's Sample Rate
BRM Fs
30
HRM
60
MCLK Frequency
(Note 14)
3.84
MCLK Duty Cycle
BRM
MCLK =128, 384 Fs
40
MCLK = 256, 512 Fs
40
HRM
MCLK = 64, 192 Fs
40
MCLK = 128, 256 Fs
40
RST Low Time
(Note 15)
1
Typ Max Units
-
50
kHz
-
100
kHz
-
25.6 MHz
50
60
%
50
60
%
50
60
%
50
60
%
-
-
ms
SCLK Falling Edge to SDOUT Output Valid
LRCK Edge to MSB Valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
SCLK Period BRM
(Note 16) t_dpd
t_lrpd
t_ds
t_dh
(Note 17) t_sck
-
-
-
-
(^{---1---2----81---})^---F----s-
-
50
ns
20
ns
10
ns
30
ns
-
ns
SCLK Period HRM
(Note 17) t_sck
--------1----------
-
( 64 ) F s
-
ns
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
t_mslr
+10
-
ns
50
-
%
Slave Mode
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge
LRCK Edge to SCLK Rising
t_sckh
50
t_sckl
50
t_lrckd
25
t_lrcks
25
-
-
ns
-
-
ns
-
-
ns
-
-
ns
Notes: 14. See Cl1:0 register on page 22 for settings.
15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks
are settled.
16. Scales with sample rate Fs. 50 ns valid at 48 kHz, more time at slower Fs and less time at faster Fs.
17. See DCK1:0 register on page 25 for settings.
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