CS4228A_03 Datasheet, PDF (11/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)
Parameter
Symbol
Min
I²C Mode (SDOUT < 47 kΩ to ground)
SCL Clock Frequency
f_scl
-
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low Time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 20)
t_hdd
0
SDA Setup Time to SCL Rising
t_sud
250
Rise Time of Both SDA and SCL Lines
(Note 21)
t_r
Fall Time of Both SDA and SCL Lines
t_f
Setup Time for Stop Condition
t_susp
4.7
Max
Units
100
kHz
µs
µs
µs
µs
µs
µs
ns
30
ns
300
ns
µs
Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
21. Pin 11 (SCL/CCLK) of the CS4228A does not have sufficient hysteresis to enable the use of standard
two-wire mode configurations with a resistor pull-up. This issue can be worked around by placing a
Schmitt Trigger buffer, for example a 74VHC14, on the SCL line just prior to the CS4228A. See Figure 5.
This will not affect the operation of the bus in either mode, as pin 6 is an input only.
Stop S ta rt
R e p e a te d
S ta rt
SDA
t _buf
t _hdst
t _high
t _hdst
t_f
SCL
t _{lo w} t _hdd
t _sud
t _sust
tr
Figure 4. I²C Control Port Timing
Stop
t _susp
V+
SCL
P in 1 1
Figure 5. I²C Mode SCL Buffer Example
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