CS4228A_03 Datasheet, PDF (20/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
The CS4228A will enter a stand-by mode if the
master clock source stops for approximately 10 µs
or if the number of MCLK cycles per LRCK period
varies by more than 32. Should this occur, the con-
trol registers retain their settings.
The CS4228A will mute the analog outputs, assert
the MUTEC pin and enter the Power Down Mode
if the supply drops below approximately 4V.
3.10 Power Supply, Layout, and
Grounding
The CS4228A requires careful attention to power
supply and grounding details. VA is normally sup-
plied from the system 5 VDC analog supply. VD is
from a 5 VDC digital supply. VL should be from
the supply used for the devices digitally interfacing
with the CS4228A. Attention should be placed on
the VL and VD power up sequence such that the
VD supply is applied at the same time or after VL
supply is applied (see “Specified Operating Condi-
tions” on page 4).
AGND and DGND pins should both be tied to a
solid ground plane surrounding the CS4228A. The
system analog and digital ground planes should not
be separated under normal circumstances. A solid
ground plane underneath the part is recommended.
Decoupling capacitors should be mounted and
routed in such a way as to minimize the circuit path
length from the CS4228A supply pin or FILT pin,
through the capacitor, and back to the applicable
CS4228A AGND or DGND pin. The small value
ceramic capacitors should be closest to the part. In
some cases, ferrite beads in the VL, VD and VA
supply lines, and low-value resistances (~ 50 Ω) in
series with the LRCK, SCLK, SDIN and SDOUT
lines can help reduce coupling of digital signals
into the analog portions of the CS4228A.
Both capacitors on the FILT pin should be as close
to the CS4228A as possible. Any noise that couples
onto the FILT pin will couple directly onto all of
the analog outputs. Please see the CDB4228 evalu-
ation board data sheet for recommended layout of
the decoupling components.
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