CS4228A_03 Datasheet, PDF (26/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
6. PIN DESCRIPTION
Serial Audio Data In 3
Serial Audio Data In 2
SDIN3 ₁ ²⁸
SDIN2 ₂ ²⁷
Serial Audio Data In 1
SDIN1 _{3 26}
Serial Audio Data Out SDOUT _{4 25}
Serial Clock
SCLK _{5 24}
Left/Right Clock
LRCK _{6 23}
Digital Ground
DGND _{7 22}
Digital Power
VD _{8 21}
Digital Interface Power
VL _{9 20}
Master Clock
MCLK _{10 19}
SCL/CCLK SCL/CCLK _{11 18}
SDA/CDIN SDA/CDIN _{12 17}
AD0/CS AD0/CS _{13 16}
Reset
RST _{14 15}
SUB
Analog Out #6,Subwoofer
CENTER Analog Out #5, Center
SR
Analog Out #4, Surround Right
SL
Analog Out #3, Surround Left
FR
Analog Out #2, Front Right
FL
Analog Out #1, Front Left
AGND Analog Ground
VA
Analog Power
AINL+ Left Channel Analog Input+
AINL- Left Channel Analog Input-
FILT
Internal Voltage Filter
AINR- Right Channel Analog Input-
AINR+ Right Channel Analog Input+
MUTEC Mute Control
SDIN1, SDIN2,
SDIN3
SDOUT
SCLK
1, 2, 3
4
5
Serial Audio Data In (Input) - Two's complement MSB-first serial audio data is input on this
pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the Left/Right clock,
serial clock and serial data is defined by the Serial Mode Register. The options are detailed
in Figures 10, 11, 12, and 13.
Serial Audio Data Out (Output) - Two's complement MSB-first serial data is output on this
pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by
the Left/Right clock. The required relationship between the Left/Right clock, serial clock and
serial data is defined by the Serial Mode Register. The options are detailed in Figures 10,
11, 12 and 13.
The state of the SDOUT pin during reset is used to set the Control Port Mode (I²C or SPI).
When RST is low, SDOUT is configured as an input, and the rising edge of RST latches the
state of the pin. A weak internal pull up is present such that a resistive load less than 47 kΩ
will pull the pin low, and the control port mode is I²C. When the resistive load on SDOUT is
greater than 47 kΩ during reset, the control port mode is SPI.
Serial Clock (Bidirectional) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,
and out of the SDOUT pin. The pin is an output in master mode, and an input in slave
mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate
SCLK at the desired multiple of the sample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally,
or the pin can be grounded and the serial clock derived internally from MCLK.
The required relationship between the Left/Right clock, serial clock and serial audio data is
defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12
and 13.
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