CS4228A_03 Datasheet, PDF (23/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
DACPDN12
DACPDN34
DACPDN56
Power down the analog section of DAC 1 and 2
*0 -
Normal
1-
Power down DAC 1 and 2.
Power down the analog section of DAC 3 and 4
*0 -
Normal
1-
Power down DAC 3 and 4.
Power down the analog section of DAC 5 and 6
*0 -
Normal
1-
Power down DAC 5 and 6.
5.4 ADC Control
Address 0x03
7
6
5
4
3
2
1
0
MUTL
MUTR
HPF
HPFZ
RESERVED
0
0
0
0
0
0
0
0
MUTL, MUTR
HPF
HPFZ
ADC left and right channel mute control
*0 -
Normal
1-
Selected ADC output muted
ADC DC offset removal. See “High Pass Filter” for more information
*0 -
Enabled
1-
Disabled
ADC DC offset averaging freeze. See “High Pass Filter” for more information
*0 -
Normal. The DC offset average is dynamically calculated and subtracted from in-
coming
ADC data.
1-
Freeze. The DC offset average is frozen at the current value and subtracted from
incoming ADC data. Allows passthru of DC information.
5.5 DAC Mute1 Control
Address 0x04
7
MUT6
1
6
MUT5
1
5
MUT4
1
4
MUT3
1
3
MUT2
1
2
MUT1
1
1
RMP1
0
0
RMP0
0
MUT6 - MUT1
RMP1:0
Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally
attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu-
ation value returns to the value stored in the corresponding Digital Volume Control register. The
attenuation value is ramped up and down at the rate specified by RMP1:0.
0-
Normal output level
*1 -
Selected DAC output fully attenuated.
Attenuation ramp rate.
*0 -
0.5 dB change per 4 LRCKs
1-
0.5 dB change per 8 LRCKs
2-
0.5 dB change per 16 LRCKs
3-
0.5 dB change per 32 LRCKs
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