CS4228A_03 Datasheet, PDF (19/32 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228A
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
0 0 1 0 0 0 AD0 0
INCR 6 5 4 3 2 1 0
76
ACK
ACK
START
10
76
ACK
10
Figure 15. Control Port Timing, I²C Slave Mode Write
DATA +n
76 10
ACK
STOP
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
0 0 1 0 0 0 AD0 0
INCR 6
START
ACK
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1
5 4 3210
0 0 1 0 0 0 AD0 1
7
0
7
0
ACK
ACK
ACK
START
DATA + n
7
0
NO
ACK _STOP
Figure 16. Control Port Timing, I²C Slave Mode Read
Since the read operation can not set the MAP, an
aborted write operation is used as a preamble. As
shown in Figure 16, the write operation is aborted
after the acknowledge for the MAP byte by sending
a stop condition. The following pseudocode illus-
trates an aborted write operation followed by a read
operation.
Send start condition.
Send 001000x0 chip address & write operation.
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 001000x1 chip address & read operation.
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows
successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.
3.8 Control Port Bit Definitions
All registers are read/write, except the Chip Status
register which is read-only. For more detailed in-
formation, see the bit definition tables.
3.9 Power-up/Reset/Power Down Mode
Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re-
set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.
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