|
CS42448 Datasheet, PDF (68/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC | |||
|
◁ |
14 REVISION HISTORY
Revision
Date
A1
July 2004
A2
October 2004
PP1
January 2005
PP2
February 2005
Changes
Initial Release
Corrected I²C Address in section 4.7.2 on page 39.
Corrected Chip I.D. in section 6.2.1 on page 44.
Initial Preliminary Product (PP) Release subject to legal notice below.
Added pin numbers to âTypical Connection Diagramâ on page 10.
Changed ADC TDM, Double-Speed Mode parameters. See Note 2 on page 11
and Note 18 on page 21.
Added ADC3 MUX Interchannel Isolation characteristic in section âCharacter-
istics and Specificationsâ beginning on page 11.
Changed SCLK Falling Edge to ADC_SDOUT Output Valid (tdpd) maximum
specification to 35 ns in section âCharacteristics and Specificationsâ beginning
on page 11.
Changed ADC Passband Ripple maximum specifications for SSM, DSM &
QSM in section âCharacteristics and Specificationsâ beginning on page 11.
Changed DAC Frequency Response specifications for SSM, DSM & QSM in
section âCharacteristics and Specificationsâ beginning on page 11.
Changed ADC Quad-Speed Mode parameters. See Note 19 on page 21.
Added section âDe-Emphasis Filterâ on page 31.
Added SCLK/LRCK & MCLK/LRCK ratio parameters in Tables 5 - 8 on page
33.
Corrected section âTDMâ on page 35.
Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB
to -64 dB) in register âAINx Volume Control (AINx_VOL[7:0])â on page 53.
Removed the âError Mode (MODE[1:0])â control bits from register âStatus Con-
trol (address 18h)â on page 54. See âInterrupt Pin Control (INT[1:0])â on
page 54, âADC CLOCK ERROR (ADC_CLK Error)â on page 54 and âADC
Overflow (ADCX_OVFL)â on page 55 for the Active Mode setting.
Corrected Figures 27-29.
Added section âOrdering Informationâ on page 67.
Table 16. Revision History
68
DS648PP2
|
▷ |