CS42448 Datasheet, PDF (23/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE
(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 21)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
(Note 22)
t_rc
-
Fall Time SCL and SDA
(Note 22)
t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
t_ack
300
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
1000
ns
Notes: 21. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
22. Guaranteed by design.
RST
t _irs
Stop
Start
SDA
SCL
t _buf
t _hdst
t _high
t
low
t
hdd
t _sud t _ack
Repeated
S ta rt
t _rd
t _hdst
Stop
t _fd
t _fc
t _susp
t _sust
t _rc
Figure 8. Control Port Timing - I²C Format
DS648PP2
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