CS42448 Datasheet, PDF (40/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive reg-
isters. Each byte is separated by an acknowledge bit.
4.8 Interrupts
The CS42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter-
rupt input pin on the host microcontroller. The INT pin may be configured as an active low or active high
CMOS driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with mul-
tiple peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Status
(address 19h) (Read Only)” on page 54. Each source may be masked off through mask register bits. In
addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option
of level sensitive or edge sensitive modes within the microcontroller, many different configurations are
possible, depending on the needs of the system designer.
4.9 Recommended Power-up Sequence
1) Hold RST low until the power supply is stable. In this state, the control port is reset to its de-
fault settings and VQ will remain low.
2) Bring RST high. The device will initially be in a low power state with VQ low. All features will
default as described in the “Register Quick Reference” on page 42.
3) Perform a write operation to the Power Control register (“Power Control (address 02h)” on
page 45) to set bit 0 to a ‘1’b. This will place the device in a power down state.
4) Load the desired register settings while keeping the PDN bit set to ‘1’b.
5) Start MCLK to the appropriate frequency, as discussed in section 4.4 on page 32. The device
will initiate the power up sequence.
6) Set the PDN bit in the power control register to ‘0’b. VQ will ramp to approximately VA/2 ac-
cording to the Popguard^® specification in section Note 4.3.3 on page 30.
7) Apply ADC/DAC_LRCK, ADC/DAC_SCLK and DAC_SDINx. Following approximately 2000
sample periods, the device is initialized and ready for normal operation.
4.10 Reset and Power-up
It is recommended that reset be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power glitch related issues.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the ADC/DAC_FILT+
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