CS42448 Datasheet, PDF (28/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

on page 49 for all bit selections. Refer to Figure 11 on page 27 for the internal ADC3 analog input
topology.
4.2.3 High Pass Filter and DC Offset Calibration
The high pass filter continuously subtracts a measure of the DC offset from the output of the dec-
imation filter. If the high pass filter is disabled during normal operation, the current value of the
DC offset for the corresponding channel is frozen and this DC offset will continue to be subtract-
ed from the conversion result. This feature makes it possible to perform a system DC offset cal-
ibration by:
1) Running the CS42448 with the high pass filter enabled until the filter settles. See the Digital
Filter Characteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
The high pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3
can be independently enabled and disabled. The high pass filters are controlled using the
HPF_FREEZE bit in the register “ADC Control & DAC De-emphasis (address 05h)” on page 49.
4.3 Analog Outputs
4.3.1 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 12 on page 29. The
CS42448 enters a Power-Down state upon initial power-up. The interpolation & decimation fil-
ters, delta-sigma modulators and control port registers are reset. The internal voltage reference,
multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass fil-
ters are powered down.
The device will remain in the Power-Down state until the RST pin is brought high. The control
port is accessible once RST is high and the desired register settings can be loaded per the in-
terface descriptions in the “Control Port Description and Timing” on page 38.
Once MCLK is valid, VQ will ramp up to VA/2, and the internal voltage references, FILT+_ADC
and FILT+_DAC, will begin powering up to normal operation. Power is applied to the D/A convert-
ers and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage,
VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine
the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal opera-
tion begins.
4.3.2 Output Transient Control
The CS42448 uses Popguard^® technology to minimize the effects of output transients during
power-up and power-down. This technique eliminates the audio transients commonly produced
by single-ended single-supply converters when it is implemented with external DC-blocking ca-
pacitors connected in series with the audio outputs. To make best use of this feature, it is nec-
essary to understand its operation. See “Popguard®” on page 30 for details.
A Mute Control pin is also available for use with an optional mute circuit to mask output tran-
sients on the analog outputs. See “Mute Control” on page 30 for details.
When changing clock ratio or sample rate it is recommended that zero data (or near zero data)
be present on DAC_SDINx for at least 10 LRCK samples before the change is made. During the
clocking change the DAC outputs will always be in a zero data state. If no zero audio is present
at the time of switching, a slight click or pop may be heard as the DAC output automatically goes
to it’s zero data state.
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