CS42448 Datasheet, PDF (21/70 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out CODEC

Parameters (Note 20)
Symbol Min
Master Mode
Output Sample Rate (LRCK)
LRCK Duty Cycle
All Speed Modes F_s
-
45
SCLK Frequency
-
SCLK Duty Cycle
45
LRCK Edge to SCLK Rising Edge
SCLK Falling Edge to ADC_SDOUT Output Valid
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
t_lcks
-
t_dpd
-
t_ds
3
t_dh1
5
Max
Units
MCLK / 256
55
64 x Fs
55
5
35
-
-
kHz
%
MHz
%
ns
ns
ns
ns
Notes: 16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled.
17. See Table 10 on page 46 and Table 11 on page 47 for suggested MCLK frequencies.
18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only.
19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified
and Time Division Multiplexed interface formats only.
20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively.
LRCK
t_lcks
SCLK
DAC_SDINx
ADC_SDOUTx
t_ds
t_dh
MSB
t_dpd
MSB
MSB-1
MSB-1
Figure 6. Serial Audio Interface Master Mode Timing
DS648PP2
21