WM8918 Datasheet, PDF (67/176 Pages) Cirrus Logic – Ultra Low Power DAC for Portable Audio Applications

Production Data
WM8918
REGISTER
ADDRESS
R94 (5Eh)
Analogue
Lineout 0
BIT
LABEL
DEFAULT
DESCRIPTION
7 LINEOUTL_RMV_
0
Removes LINEOUTL short
SHORT
0 = LINEOUTL short enabled
1 = LINEOUTL short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTL Enable sequence.
6
LINEOUTL_ENA_
0
Enables LINEOUTL output stage
OUTP
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
5
LINEOUTL_ENA_
0
Enables LINEOUTL intermediate
DLY
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTL_ENA.
4
LINEOUTL_ENA
0
Enables LINEOUTL input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTL Enable sequence.
3
LINEOUTR_RMV
_SHORT
0
Removes LINEOUTR short
0 = LINEOUTR short enabled
1 = LINEOUTR short removed
For normal operation, this bit should
be set as the final step of the
LINEOUTR Enable sequence.
2 LINEOUTR_ENA_
0
Enables LINEOUTR output stage
OUTP
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
1 LINEOUTR_ENA_
0
Enables LINEOUTR intermediate
DLY
stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after LINEOUTR_ENA.
0
LINEOUTR_ENA
0
Enables LINEOUTR input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set as the first step of the
LINEOUTR Enable sequence.
Table 41 Headphone / Line Output Pop Suppression Control
w
PD, Rev 4.1, January 2012
67