WM8918 Datasheet, PDF (20/176 Pages) Cirrus Logic – Ultra Low Power DAC for Portable Audio Applications

WM8918
SLAVE MODE
BCLK (input)
LRCLK (input)
AIFTXDAT
(output)
AIFRXDAT
(input)
t_BCY
t_BCH
t_BCL
t_LRH
t_LRSU
t_DD
t_DS
t_DH
Figure 3 Audio Interface Timing – Slave Mode
Production Data
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, T_A = +25^oC, Slave Mode, fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Interface Timing - Slave Mode
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
AIFRXDAT hold time from BCLK rising edge
AIFTXDAT propagation delay from BCLK falling edge
AIFRXDAT set-up time to BCLK rising edge
SYMBOL
t_BCY
t_BCH
tBCL
tLRSU
t_LRH
t_DH
tDD
tDS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
20
ns
10
ns
10
ns
20
ns
20
ns
Note: BCLK period must always be greater than or equal to MCLK period.
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PD, Rev 4.1, January 2012
20