WM8918 Datasheet, PDF (22/176 Pages) Cirrus Logic – Ultra Low Power DAC for Portable Audio Applications

WM8918
CONTROL INTERFACE TIMING
Production Data
Figure 5 Control Interface Timing
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA=+25^oC, Slave Mode, fs=48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDA, SCLK Rise Time
SDA, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SYMBOL
t₁
t2
t3
t₄
t₅
t6
t7
t₈
t₉
tps
MIN
1300
600
600
600
100
600
0
TYP
MAX
400
300
300
900
5
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD, Rev 4.1, January 2012
22