WM8918 Datasheet, PDF (65/176 Pages) Cirrus Logic – Ultra Low Power DAC for Portable Audio Applications

Production Data
SEQUENCE
Step 1
Step 2
Step 3
HEADPHONE ENABLE
HPL_ENA = 1
HPR_ENA = 1
HPL_ENA_DLY = 1
HPR_ENA_DLY = 1
DC offset correction
Step 4
Step 5
HPL_ENA_OUTP = 1
HPR_ENA_OUTP = 1
HPL_RMV_SHORT = 1
HPR_RMV_SHORT = 1
Table 39 Headphone / Line Output Enable Sequence
WM8918
LINEOUT ENABLE
LINEOUTL_ENA = 1
LINEOUTR_ENA = 1
LINEOUTL_ENA_DLY = 1
LINEOUTR_ENA_DLY = 1
DC offset correction
LINEOUTL_ENA_OUTP = 1
LINEOUTR_ENA_OUTP = 1
LINEOUTL_RMV_SHORT = 1
LINEOUTR_RMV_SHORT = 1
SEQUENCE
Step 1
Step 2
HEADPHONE DISABLE
HPL_RMV_SHORT = 0
HPR_RMV_SHORT = 0
HPL_ENA = 0
HPL_ENA_DLY = 0
HPL_ENA_OUTP = 0
HPR_ENA = 0
HPR_ENA_DLY = 0
HPR_ENA_OUTP = 0
Table 40 Headphone / Line Output Disable Sequence
LINEOUT DISABLE
LINEOUTL_RMV_SHORT = 0
LINEOUTR_RMV_SHORT = 0
LINEOUTL_ENA = 0
LINEOUTL_ENA_DLY = 0
LINEOUTL_ENA_OUTP = 0
LINEOUTR_ENA = 0
LINEOUTR_ENA_DLY = 0
LINEOUTR_ENA_OUTP = 0
The registers relating to Headphone / Line Output pop suppression control are defined in Table 41.
REGISTER BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
R90 (5Ah)
7 HPL_RMV_SHOR
0
Removes HPL short
Analogue
T
0 = HPL short enabled
HP 0
1 = HPL short removed
For normal operation, this bit should
be set as the final step of the HPL
Enable sequence.
6
HPL_ENA_OUTP
0
Enables HPL output stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the DC offset
cancellation has been scheduled.
5
HPL_ENA_DLY
0
Enables HPL intermediate stage
0 = Disabled
1 = Enabled
For normal operation, this bit should
be set to 1 after the output signal path
has been configured, and before DC
offset cancellation is scheduled. This
bit should be set with at least 20us
delay after HPL_ENA.
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PD, Rev 4.1, January 2012
65