CS4227 Datasheet, PDF (6/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
SWITCHING CHARACTERISTICS (T_A = 25 °C; VA+, VD+ = +5 V ±5%; outputs loaded with 30 pF.)
Parameter
Symbol Min
Typ
Max Unit
Audio ADC’s and DAC’s Sample Rate
Fs
4
-
50
kHz
XTI Frequency
XTI = 256, 384, or 512 Fs
1.024
-
26
MHz
XTI Pulse Width High
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
-
21
-
31
-
-
ns
-
-
XTI Pulse Width Low
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
10
-
21
-
31
-
-
ns
-
-
XTI Jitter Tolerance
-
500
-
ps
CLKOUT Jitter
(Note 9)
-
200
- psRMS
CLKOUT Duty Cycle (high timer/cycle time)
(Note 10)
40
50
60
%
PDN Low Time
(Note 11)
500
-
-
ns
SCLK Falling Edge to SDOUT Output Valid
DSCK = 0 t_dpd
-
- Note 12 ns
LRCK edge to MSB valid
t_lrpd
-
-
40
ns
SDIN Setup Time Before SCLK Rising Edge
DSCK = 0
t_ds
-
-
25
ns
SDIN Hold Time After SCLK Rising Edge
DSCK = 0
t_dh
-
-
25
ns
Master Mode
SCLK Falling to LRCK Edge
SCLK Period
DSCK = 0 t_mslr
(Note 14)
-
-
±10
-
ns
-
-
-
-
SCLK Duty Cycle
-
50
-
%
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
t_sckw
Note 13
-
t_sckh
40
-
t_sckl
40
-
DSCK = 0 t_lrckd
20
-
DSCK = 0 t_lrcks
40
-
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN should be held low for 1 ms to allow the power supply to settle.
12. ----------1----------- + 20
( 384 ) Fs
13. -₍--1---2----81---₎---F---s--
14. _{-(--2---5--6-1--)---F---s--}
6
DS281PP2