CS4227 Datasheet, PDF (23/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
2.16 Converter Control Byte (2)
7
6
5
4
3
2
1
CALP
CLKE
DU
0
0
0
CAL
RS
Chip reset
0 - No Reset
1 - Reset
CAL
Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
The following bits are read only:
DU
Shows selected De-Emphasis setting used by DAC’s
0 - Normal Flat DAC frequency response
1 - De-Emphasis selected
CLKE
Clocking system status
0 - No errors
1 - Crystal is not oscillating, or requesting clock change in progress
CALP
Calibration status
0 - Calibration done
1 - Calibration in progres
This register defaults to 01h.
2.17 DAC Control Byte (3)
7
ZCD
6
MUTC
5
MUT6
4
MUT5
3
MUT4
2
MUT3
1
MUT2
MUT6-MUT1
Mute control bits
0 - Normal output level
1 - Selected DAC output muted
MUTC
Controls mute on consecutive zeros function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros
ZCD
Zero crossing disable
0 - DAC mutes and volume control changes occur on zero-crossings
1 - DAC mutes and volume control changes occur immediately.
This register defaults to 3Fh.
0
RS
0
MUT1
DS281PP2
23