CS4227 Datasheet, PDF (26/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
2.23 DSP Port Mode Byte (14)
7
DCK1
6
DCK0
5
DMS1
4
DMS0
3
DSCK
2
DDF2
1
DDF1
DDF2-DDF0
Data format
0 - Right justified, 20-bit
1 - Right justified, 18-bit
2 - Right justified, 16-bit
3 - Left justified, 20-bit in / 24-bit out
4 - I²S compatible, 20-bit in / 24-bit out
5 - One Data Line Mode (Figure 10)
6 - One Data Line (Master Mode only, Figure 10)
7 - Not used
DSCK
Set the polarity of clocking data
0 - Data clocked in on rising edge, out on falling edge
1 - Data clocked in on falling edge, out on rising edge
DMS1-DMS0
Sets the mode of the port
0 - Slave
1 - Master Burst - SCLKs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKs are evenly distributed (No 48 Fs SCLK)
3 - not used - default to Slave
DCK1-DCK0*
Set number of bit clocks per Fs period
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All formats will default to 16 bits
3 - 64
This register defaults to 00h.
* Ignored in data formats 5 and 6.
0
DDF0
26
DS281PP2