CS4227 Datasheet, PDF (14/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
2.3.2 Output Level Attenuator
The DAC outputs are each routed through an atten-
uator which is adjustable in 1 dB steps. Output at-
tenuation is available through the Output
Attenuator Data Bytes. Level changes are imple-
mented such that the noise is attenuated by the
same amount as the signal (equivalent to using an
analog attenuator after the signal source) until the
residual output noise is equal to the noise floor in
the mute state. Level changes only take effect on
zero crossings to minimize audible artifacts. If
there is no zero crossing, then the requested level
change will occur after a time-out period between
512 and 1024 frames (11.6 ms to 23.2 ms at
44.1 kHz frame rate). There is a separate zero
crossing detector for each channel. Each ACC bit
in the DAC Status Report Byte provides informa-
tion on when a volume control change has taken ef-
fect. This bit goes high when a new setting is
loaded and returns low when it has taken effect.
Volume control changes can be instantaneous by
setting the Zero Crossing Disable (ZCD) bit in the
DAC Control Byte (#3) to 1.
Each output can be independently muted via mute
control bits, MUT6-1, in the DAC Control Byte
(#3). The mute also takes effect on a zero-crossing
or after a timeout. In addition, the CS4227 has an
optional mute on consecutive zeros feature, where
all DAC outputs will mute if they receive between
512 and 1024 consecutive zeros (or -1 code) on all
six channels. A single non-zero value will unmute
the DAC outputs. This feature can be disabled with
the MUTC bit in the DAC Control Byte (#3).
2.4 Clock Generation
The master clock to operate the CS4227 may be
generated by using the on-chip inverter and an ex-
ternal crystal or by using an external clock source.
If the active clock source stops for 10 µs, the
CS4227 will enter a power down state. In all modes
it is required to have SCLK and LRCK synchro-
nous to the selected master clock.
2.4.1 Clock Source
The CS4227 requires a high frequency master
clock to run the internal logic. The clock enable bit
(CE) must be set to 0 after power-up of the device
(see Power-up/Reset/Power Down Mode section).
A high frequency crystal can be connected to XTI
and XTO, or a high frequency clock can be applied
to XTI. This high frequency clock can be 256 Fs,
384 Fs or 512 Fs; this is set by the CI0/1 bits in the
Clock Mode Byte (#1). When using the on-chip
crystal oscillator, external loading capacitors are
required (see Figure 5). High frequency crystals
(>8 MHz) should be parallel resonant, fundamental
mode and designed for 20 pF loading (equivalent to
40 pF to ground on each leg).
2.4.2 Master Clock Output
CLKOUT is a master clock output provided to al-
low synchronization of external components.
Available CLKOUT frequencies of 1 Fs, 256 Fs,
384 Fs, and 512 Fs, are selectable by the CO0/1 bits
of the Clock Mode Byte.
Generation of CLKOUT for 384 Fs and 512 Fs is
accomplished with an on chip clock multiplier and
may contain clock jitter. The source of the 256 Fs
CLKOUT is a divided down clock from the
XTI/XTO input. If 384 Fs is chosen as the input
clock at XTI and 256 Fs is chosen as the output,
CLKOUT will have approximately a 33% duty cy-
cle. In all other cases CLKOUT will typically have
a 50% duty cycle.
2.4.3 Synchronization
The DSP port and Auxiliary port must operate syn-
chronously to the CS4227 clock source. The serial
port will force a reset of the data paths in an attempt
to resynchronize if non-synchronous data is input
to the CS4227. It is advisable to mute the DACs
when changing from one clock source to another to
avoid the output of undesirable audio signals as the
CS4227 resynchronizes.
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DS281PP2