CS42888 Datasheet, PDF (50/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
6.14.2 ADC CLOCK ERROR (ADC_CLK ERROR)
Default = x
Function:
Indicates an invalid MCLK to ADC_LRCK ratio. This status flag is set to “Level Active Mode” and becomes
active during the error condition. See “System Clocking” on page 29 for valid clock ratios.
6.14.3 ADC Overflow (ADCX_OVFL)
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42888 ADC signal path of each of the
associated ADC’s. These status flags become active on the arrival of the error condition.
6.15 Status Mask (Address 1Ah)
7
Reserved
6
Reserved
5
Reserved
4
DAC_CLK
Error_M
Default = 00000
3
ADC_CLK
Error_M
2
Reserved
1
ADC2_OVFL_M
0
ADC1_OVFL_M
Function:
The bits of this register serve as a mask for the error sources found in the register “Status (Address 19h)
(Read Only)” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will
affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its oc-
currence will not affect the INT pin or the status register. The bit positions align with the corresponding bits
in the Status register.
6.16 MUTEC Pin Control (Address 1Bh)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
1
Reserved MCPolarity
0
MUTEC
ACTIVE
6.17 MUTEC Polarity Select (MCPOLARITY)
Default = 0
0 - Active low
1 - Active high
Function:
Determines the polarity of the MUTEC pin.
6.18 MUTE CONTROL ACTIVE (MUTEC ACTIVE)
Default = 0
0 - MUTEC pin is not active.
1 - MUTEC pin is active.
Function:
The MUTEC pin will go high or low (depending on the MUTEC Polarity Select bit) when this bit is enabled.
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