CS42888 Datasheet, PDF (29/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
De-emphasis is only available in Single-Speed Mode. Please see “DAC De-Emphasis Control
(DAC_DEM)” on page 45 for de-emphasis control.
Gain
dB
0dB
-10dB
T1=50 µs
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 13. De-Emphasis Curve
4.4 System Clocking
The CODEC (ADC & DAC) serial audio interface ports operate both as a slave or master. The serial ports
accept externally generated clocks in slave mode and will generate synchronous clocks derived from an in-
put master clock in master mode. In the TDM format the ADC and DAC serial ports will only operate as a
slave. In OLM #2 the serial ports will accept or output a 256Fs SCLK. See the registers “DAC Functional
Mode (DAC_FM[1:0])” on page 42 and “ADC Functional Mode (ADC_FM[1:0])” on page 42 for setting up
master/slave mode.
The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be
an integer multiple of, and synchronous with, the system sample rate, Fs.
The required integer ratios, along with some common frequencies, are illustrated in tables Tables 2 to 4.
The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency
(MFREQ[2:0])” on page 42.
Sample Rate
(kHz)
32
44.1
48
Sample Rate
(kHz)
64
88.2
96
Sample Rate
(kHz)
176.4
192
DS717F1
MCLK (MHz)
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 2. Single-Speed Mode Common Frequencies
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
Table 3. Double-Speed Mode Common Frequencies
MCLK (MHz)
64x
11.2896
12.2880
96x
16.9344
18.4320
128x
22.5792
24.5760
192x
33.8688
36.8640
Table 4. Quad-Speed Mode Common Frequencies
1024x
32.7680
45.1584
49.1520
512x
32.7680
45.1584
49.1520
256x
45.1584
49.1520
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