CS42888 Datasheet, PDF (26/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
No Power
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Power-Down (Power Applied)
1. VQ = 0 V.
2. Aout = VQ.
3. No audio signal generated.
4. Control Port Registers reset
to default.
RST = Low? ^Yes
No
PDN bit = '1'b? ^Yes
No
Power-Down Mode
1. VQ = 0 V.
2. Aout bias = VQ.
3. No audio signal generated.
4. Control Port Registers retain
settings.
PopGuard^®
Power-Up Ramp
1. VQ ramp up to VA/2.
2. Aout bias = VQ.
400 ms delay
Power-Down Ramp
1. VQ ramp down to 0 V.
2. Aout bias = VQ.
250 ms delay
Control Port
Active
No
Control Port
Yes
Access Detected?
No Power Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
Hardware Mode not supported.
Codec will power up in an
unknown state once all clocks
and data are valid. It is
recommended that the user
setup up the codec via the
control port before applying
MCLK.
Power-Down Transition
1. VQ = 0 V.
2. Aout bias = VQ.
3. Audible pops.
Software Mode
Registers setup to
desired settings.
No
Valid MCLK
Applied?
Yes
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
No
Valid
MCLK/LRCK
Ratio?
Yes
2000 LRCK delay
RST = Low
ERROR: Power removed
Normal Operation
1. VQ = VA/2.
2. Aout bias = VQ.
3. Audio signal generated per register settings.
PDN bit set
to '1'b
ERROR: MCLK/LRCK ratio change
ERROR: MCLK removed
Analog Output Mute
1. VQ = VA/2.
2. Aout bias = VQ.
3. DAC outputs muted.
4. No audio signal generated.
Analog Output Freeze
1. VQ = VA/2.
2. Aout bias = VQ + last audio sample.
3. DAC Modulators stop operation.
4. Audible pops.
Figure 11. Audio Output Initialization Flow Chart
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