CS42888 Datasheet, PDF (32/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

CS42888
4.5.5 OLM #2
OLM #2 serial audio interface format operates in Single- or Double-Speed Mode and will master or slave
ADC/DAC_SCLK at 256Fs.
128 clks
128 clks
ADC/DAC_LRCK
Left Channel
Right Channel
ADC/DAC_SCLK
DAC_SDIN1
MSB
LSB MSB
LSB MSB
LSB
AOUT1
AOUT3
AOUT5
MSB
LSB MSB
LSB MSB
LSB
AOUT2
AOUT4
AOUT6
MSB
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
DAC_SDIN4
AOUT7
24 clks
AOUT8
24 clks
ADC_SDOUT1
AIN1
24 clks
AIN3
-
AIN2
AIN4
24 clks
24 clks
24 clks
24 clks
Figure 18. One-Line Mode #2 Format
-
24 clks
4.5.6
TDM
TDM data is received most significant bit (MSB) first, on the second rising edge of the DAC_SCLK occur-
ring after a DAC_LRCK rising edge. All data is valid on the rising edge of DAC_SCLK. The AIN1 MSB is
transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmit-
ted on the falling edge of ADC_SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘jus-
tified within the time slot. Valid data lengths are 16, 18, 20, or 24.
ADC/DAC_SCLK must operate at 256Fs. ADC/DAC_LRCK identifies the start of a new frame and is equal
to the sample rate, Fs.
ADC/DAC_LRCK is sampled as valid on the rising ADC/DAC_SCLK edge preceding the most significant
bit of the first data sample and must be held valid for at least 1 ADC/DAC_SCLK period.
Note: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.
ADC/DAC_LRCK
Bit or Word Wide
256 clks
ADC/DAC_SCLK
DAC_SDIN1
ADC_SDOUT1
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
AOUT7
AOUT8
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
AIN1
AIN2
AIN3
AIN4
-
-
AUX1
AUX2
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 19. TDM Format
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DS717F1