CS42888 Datasheet, PDF (24/61 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out CODEC

4. APPLICATIONS
CS42888
4.1 Overview
The CS42888 is a highly integrated mixed signal 24-bit audio CODEC comprised of 4 analog-to-digital con-
verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)
also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-
ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass
filters, an on-chip voltage reference, and Popguard technology that minimizes the effects of output tran-
sients on power-up and power-down.
All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC serial
port. Each serial port can be configured independently to operate at different sample and clock rates, but
both must run synchronous to each other.
The serial audio interface ports allow up to 8 DAC channels and 6 ADC channels in a Time-Division Multi-
plexed (TDM) interface format. In the One-Line Mode (OLM) interface format, the CS42888 will allow up to
6 ADC channels on one data line and up to 8 DAC channels on 2 data lines.
The CS42888 features an Auxiliary Port used to accommodate an additional two channels of PCM data on
the ADC_SDOUT data line in the TDM digital interface format. See “AUX Port Digital Interface Formats” on
page 33 for details.
The CS42888 operates in one of three oversampling modes based on the input sample rate. When operat-
ing the CODEC as a slave, mode selection is determined automatically based on the MCLK frequency set-
ting. When operating as a master, mode selection is determined by the ADC and DAC FM bits in register
“Functional Mode (Address 03h)” on page 42. Single-Speed Mode (SSM) supports input sample rates up
to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates
up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is only supported in the I²S,
Left-Justified, Right-Justified interface formats. QSM for the DAC is supported in the I²S, Left-Justified,
Right-Justified and Time Division Multiplexed interface formats).
All functions can be configured through software via a serial control port operable in SPI Mode or in I²C
Mode.
Figure 2 on page 16 shows the recommended connections for the CS42888. See “Register Description” on
page 40 for the default register settings and options.
4.2 Analog Inputs
4.2.1
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 10 on page 25 shows the full-scale analog input levels. The CS42888 also accommodates single-
ended signals on all inputs, AIN1-AIN4. See “ADC Input Filter” on page 51 for the recommended input
filters.
For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the register “ADC
Control & DAC De-Emphasis (Address 05h)” on page 44 must be set appropriately (see Figure 26 on
page 51 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume
Control (Address 11h-14h)” on page 48.
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