EP7311_05 Datasheet, PDF (42/58 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface

EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location
Name
V2
VSSIO
V3
VSSIO
Strength^†
Reset
State
Type
Pad ground
Pad ground
V4
PD[7]/SDQM[1]
1
Low
I/O
V5
PD[4]
V6
PD[2]
V7
SSICLK
V8
SSIRXDA
1
Low
I/O
1
Low
I/O
1
‡
Input
I/O
I/O
V9
nADCCS
1
High
O
V10
VDDIO
Pad power
V11
ADCCLK
1
Low
O
V12
COL[7]
1
High
O
V13
COL[4]
1
High
O
V14
TCLK
V15
BUZ
V16
D[29]
I
1
Low
O
1
Low
I/O
V17
A[26]/DRA[1]
2
Low
O
V18
VDDIO
Pad power
V19
VDDIO
Pad power
V20
A[24]/DRA[3]
‘
W1
VSSIO
W2
VSSIO
W3
VSSIO
Low
O
Pad ground
Pad ground
Pad ground
W4
PD[6]/SDQM[0]
1
Low
I/O
W5
W6
W7
W8
W9
W10
TMS
PD[1]
SSITXFR
SSIRXFR
VSSCORE
DRIVE[1]
with p/u*
1
1
1
2
Low
Low
‡
Input
High /
Low
I
I/O
I/O
I/O
Core Ground
I/O
Description
I/O ground
I/O ground
GPIO port D /
SDRAM byte lane
mask
GPIO port D
GPIO port D
DAI/CODEC/SSI2
serial clock
DAI/CODEC/SSI2
serial data input
SSI1 ADC chip
select
Digital I/O power,
3.3V
SSI1 ADC serial
clock
Keyboard scanner
column drive
Keyboard scanner
column drive
JTAG clock
Buzzer drive output
Data I/O
System byte address
/ SDRAM address
Digital I/O power,
3.3 V
Digital I/O power,
3.3 V
System byte address
/ SDRAM address
I/O ground
I/O ground
I/O ground
GPIO port D /
SDRAM byte lane
mask
JTAG mode select
GPIO port D
DAI/CODEC/SSI2
frame sync
DAI/CODEC/SSI2
frame sync
Core Ground
PWM drive output
42
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(All Rights Reserved)
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