EP7311_05 Datasheet, PDF (21/58 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface

EP7311
High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the
values for the timings of each of the Static Memory modes.
Parameter
EXPCLK rising edge to nCS assert delay time
EXPCLK falling edge to nCS deassert hold time
EXPCLK rising edge to A assert delay time
EXPCLK falling edge to A deassert hold time
EXPCLK rising edge to nMWE assert delay time
EXPCLK rising edge to nMWE deassert hold time
EXPCLK falling edge to nMOE assert delay time
EXPCLK falling edge to nMOE deassert hold time
EXPCLK falling edge to HALFWORD deassert delay time
EXPCLK falling edge to WORD assert delay time
EXPCLK rising edge to data valid delay time
EXPCLK falling edge to data invalid delay time
Data setup to EXPCLK falling edge time
EXPCLK falling edge to data hold time
EXPCLK rising edge to WRITE assert delay time
EXPREADY setup to EXPCLK falling edge time
EXPCLK falling edge to EXPREADY hold time
Symbol
t_CSd
t_CSh
t_Ad
t_Ah
t_MWd
t_MWh
t_MOEd
t_MOEh
t_HWd
t_WDd
t_Dv
t_Dnv
t_Ds
t_Dh
t_WRd
t_EXs
t_EXh
Min
2
2
4
3
3
3
3
2
2
2
8
6
-
-
5
-
-
Typ
8
7
9
10
6
6
7
7
8
8
13
15
-
-
11
-
-
Max
20
20
16
19
10
10
10
10
20
16
21
30
1
3
23
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS506F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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